The present invention relates to an electro-static discharge protection device, and more particularly to an electro-static discharge protection device having a low operation voltage.
Generally, a semiconductor apparatus has an electro-static discharge protection circuit located between a pad and an internal circuit for protecting the internal circuit.
The electro-static discharge protection circuit prevents a discharge phenomenon where electrostaticity is discharged to the internal circuit or is discharged externally from the internal circuit through a pad when an external pin of an integrated circuit contacts a human body or a charged machine.
A power clamp unit, as shown in FIG. 1, is used to prevent damage to the internal circuit due to the external discharge of charges from the internal circuits by maintaining a constant power voltage and ground voltage.
The power clamp unit has an NMOS transistor N1 connected between a power voltage line VDD and a ground voltage line GND. If electrostaticity is inputted from the ground voltage line, the NMOS transistor N1 is turned on to discharge the electrostaticity to a power pad through the power voltage line.
However, as semiconductor apparatuses become more highly integrated and have a lower operation voltage, a problem arises in that an internal circuit is damaged even under a low electrostatic voltage.
Meanwhile, FIGS. 2 and 3 show circuits designed for performing a CDM (Charged Device Model) to prevent electrostaticity externally discharged from the internal circuit from affecting the internal circuit.
FIG. 2 shows a capacitor C1 and a resistor R1 connected in series between the power voltage line VDD and the ground voltage GND line for lowering a trigger voltage of the NMOS transistor N1 of FIG. 1.
The power clamp unit of FIG. 2 applies a coupling voltage generated between the capacitor C1 and the resistor R1 to the NMOS transistor N1 to lower the trigger voltage of the NMOS transistor N1. The capacitor C1 may be replaced with a PMOS transistor forming a capacitor C2 as shown in FIG. 3.
However, the power clamp unit illustrated in FIGS. 2 and 3 should have a large capacitor of several pF (picofarad) for securing sheet resistance, which becomes smaller as the power clamp unit becomes more highly integrated, so that it has a problem that a large area is allocated.